As is known, present MOS microelectronics devices contain oxide layers, the thickness of which is not known with precision. In particular, the thickness of the gate oxide layer (HV oxide for high-voltage components and LV oxide for low-voltage components), which is formed on the surface of the wafer and undergoes the gate definition step, may be undefined for various reasons. First of all, the doping level of the wafer surface region is not known precisely and may vary slightly from batch to batch under the same manufacturing conditions; since the doping level affects the thickness of the oxide layer grown above the surface region (the more the surface region is doped, the greater is oxide layer the thickness) initial uncertainty arises as to the value of this thickness. Moreover, during the gate region definition step, when the polycrystalline silicon layer is etched to remove the useless silicon portions, overetching may occur, causing slight removal of the oxide layer, despite the selectivity of the etching operation. This possible removal may in turn increase the uncertainty as to the thickness. The subsequent gate region re-oxidation step, performed to seal the gate region, may further increase this uncertainty.
The fact of not knowing the thickness of the oxide layer covering the wafer surface during manufacture is disadvantageous since ion implantation steps are performed through this layer (typically for formation of drain and source regions of MOS components), the effectiveness of which (obtainable doping level, implant depth) depends on the oxide thickness. Furthermore, the device final electrical characteristics and hence its ability to pass the final test depends precisely on the conditions of this implant. Consequently, by knowing the thickness of the oxide layer through which implantation of component conductive regions is performed, it is possible to evaluate, at an early stage of the manufacturing process, whether the finished device will, with a good degree of probability, be able to pass the final test or not, eliminating any defective wafers during an early manufacture step and hence reducing the costs associated with manufacturing rejects and carrying out complex final testing steps. Alternatively, using this information it is possible, if necessary, to modify the process parameters so as to adapt them to the given oxide thickness to ensure, at least as regards the characteristics associated with the thickness of the oxide layer, that the final tests are passed.
In view of the above, there currently exists the need of a method for measuring this oxide.
At present, this need has not yet been satisfied and suitable measurement methods do not exist. In fact, the present measurements performed on test chips, for verifying correct operation of the machines for manufacturing microelectronics devices, do not provide significant results since they use substrates which are not doped or in any case have different characteristics from those of the devices intended for commercial distribution, the oxide thickness of which is to be ascertained.
Other currently known methods for measuring the oxide thickness cannot be used on-line since they require sectioning the wafer and examining the obtained section under a scanning electron microscope (SEM) or, as in case of capacitors, they require a predefined minimum thickness (greater than that of the oxide layer to be examined) and/or a large examination area, greater than the zone accommodating the oxide to be measured (typically coinciding with the source and drain regions).